The invention relates to a variable gain circuit, and more particularly, to a variable gain circuit preferred for use in a code division multiple access (CDMA) system portable telephone.
Recently, portable telephones have become very popular. A CDMA portable telephone employs a variable gain circuit as disclosed in Japanese Unexamined Patent Publication No. 9-270,649, for example.
FIG. 1 shows an example of a variable gain circuit 70 in a transmitter of the portable telephone. The variable gain circuit 70 comprises a quadrature phase shift keying (QPSK) circuit 80, a first variable gain amplifier 81 of variable drive current type, a second variable gain amplifier 83 of constant drive current type, and an up-converter 82 connected between the amplifiers 81, 83.
The QPSK circuit 80 receives I and Q signals and modulates them on an intermediate frequency (IF) transmitting signal, which is then provided to the first variable gain amplifier 81, which in turn amplifies the IF transmitting signal to feed the up-converter 82.
The up-converter 82 mixes the amplified IF signal with a local oscillator frequency to convert the amplified IF signal into a high frequency signal or RF transmitting signal, which is then fed to the second variable gain amplifier 83, which in turn amplifies the RF transmitting signal. The amplified RF transmitting signal is passed via a bandpass filter, not shown, before being delivered to an antenna.
The first variable gain amplifier 81 comprises a differential amplifier 81a and a constant current circuit 81b formed by a transistor Q3. The differential amplifier 81a comprises a pair of transistors Q1 and Q2 having their emitters connected together. Each of the transistors Q1, Q2 has a base for receiving the IF transmitting signal. The transistor Q3 has a base for receiving an AGC voltage V.sub.AGC, and the transistor Q3 controls a current I1 in accordance with the level of the voltage V.sub.AGC. The differential amplifier 81a has a gain Ga which varies with a change in the current I1 in a manner graphically shown in FIG. 2(a).
The second variable gain amplifier 83 comprises a differential amplifier 83a, a constant current circuit 83b, and first and second current mirror circuits 83c, 83d. The differential amplifier 83a includes pairs of gain changing transistors Q11, Q12 and Q13, Q14 with the emitters of each pair connected together, and amplifying transistors Q15, Q16. The first current mirror circuit 83c includes a transistor Q19 in combination with the transistors Q11, Q14. The second current mirror circuit 83d includes a pair of transistors Q17, Q20 having their bases connected together and connected to the collector of the transistor Q20. A transistor Q18 is connected to the collector of the transistor Q20.
Each of the transistors Q15, Q16 has a base for receiving the RF transmitting signal, and the transistor Q18 has a base for receiving the voltage V.sub.AGC. Thus, a collector current of the transistor Q18 is controlled in accordance with the level of the voltage V.sub.AGC. A collector current of each of the transistors Q11, Q14 is proportional to the collector current of the transistors Q18. In other words, the collector current of each of the transistors Q11, Q14 is controlled in accordance with the level of the voltage V.sub.AGC, whereby a gain Gb of the differential amplifier 83a varies in a manner graphically shown in FIG. 2(b).
As may be seen from FIG. 2(a), a response of the first variable gain amplifier 81 exhibits excellent linearity toward a higher gain, but is distorted toward a lower gain. This represents a problem which is common to variable gain amplifiers of variable drive current type. On the other hand, as may be seen from FIG. 2(b), a response of the second variable gain amplifier 83 exhibits an excellent linearity toward a lower gain, but is distorted toward a higher gain. This represents another problem which is common to variable gain amplifiers of constant drive current type.
Because the variable gain circuit 70 includes both the first and second variable gain amplifiers 81, 83, a total gain response G contains distortions toward both a lower and a higher gain, as graphically shown in FIG. 2(c), thus degrading the linearity of the total gain of the variable gain circuit 70.
It is an object of the present invention to provide a variable gain circuit having a highly linear gain response.